View as HTML KAL Silicon Technologies

Dear ,

We are happy to share this important article with you, Written by Mr. Ganesh Lokunde, Senior Engineer, Physical Design, Eteros Technologies

____________________________________________________________________________

Synthesis to Signoff:
Tackling Real-Time Issues in STA, SDC, PNR & More

Ganesh Lokunde, Senior Engineer, Physical Design, Eteros Technologies

Table of Contents
1. Register to Clock Gating Timing violations and fixing!
2. Clock Gating Cells & related Timing Constraints
3. Logically Exclusive Clock Groupings
4. Combinational Loops and their impact on timing
5. PBA in shift corners
6. Defining Skew Groups before CTS with the help of SDC?
7. Miscellaneous: Script to find out the flop with best library Hold Time

------------------------------------------------------------------------------------

1. Register to Clock Gating Timing violations and fixing!

Background
ICG are used in the place of normal Clock Gaters as they can help avoid glitches in the Clock reaching the Flops. ICG’s are helpful in the design to reduce the Dynamic Power consumption by gating the Clock reaching the Clock pin of the flops when the data reaching the flop is not switching.

Problem Statement
We have a Reg2ClkGate setup violations and there are no cells in the enable path reaching the EN pin of CG. We must fix the setup violation either by pushing the clock reaching the CP pin of CG or pull the clock at launch flipflop.

For the problem in hand let’s focus on the impact of clock pushing.

Output of the ICG reaches a lot of flops to which it is gating the clock. Thus, pushing the CP pin of CG indirectly pushes all the flops which are in the fanout of the ICG. Thus, we can’t blindly push the clocks unless we are sure about the impact it has on all the flops in the fanout.

As shown in figure 1. We have added “Pre-Fanout Flops” & “Post-Fanout Flops”. Timing paths launching from Pre-Fanout flops & Also timing paths captured at Post Fanout flops are also affected due to clock push at the CG.

Data launched from “Pre Fanout flops” is getting captured at the “Fanout Flops”. Data launched from “Fanout flops” are being captured at the “Post Fanout flops”.

Proposed Solution
Clock Pushing at CG indirectly pushes the Clock reaching all the “Fanout Flops”. Thus, two new sets of timing paths must be considered and checked.

First Set – Paths with data launching from “Pre Fanout Flops” & capturing at “Fanout Flops” Second Set – Paths data launching from “Fanout Flops” and Capturing at “Post Fanout Flops”

If Clock is pushed at Clock Gater’s clock pin to resolve setup violations, below 3 setup of timing paths must be checked.

1. Hold timing to the “First Set” as mentioned above. As we are indirectly pushing the Clock reaching “Fanout Flops” These aids in Setup time of “First Set” but worsens Hold time.
report_timing -to <Fanout Flops/D> -early

2. Setup Timing to the “Second Set”. As Pushing CG CP pin indirectly pushes the “Fanout Flops”. This aids in Hold timing of Second Set but worsens Setup.
report_timing -through <Fanout Flops/CP> -late

3. Hold Time of “Register” to “CG” checks.

Request the full article