Dear ,
In this eNews, we would like to provide with a short overview of the advanced JESD204 IP cores brought to you by our partner Comcores
Overview
The JESD204C controller IP is a highly optimized and silicon agnostic implementation of the JEDEC JESD204C standard targeting any ASIC, FPGA or ASSP technologies. The IP-core supports line speeds up to 32 Gbps per lane and includes full backwards compatibility with JESD204B.
The IP core enables quick and reliable deployment of both the transmitter (TX) and the receiver (RX) link layer and comes optionally with a tightly integrated transport layer option. The IP comes with the widest parameter set available and has gone through extensive testing.The IP-core is silicon proven, heavily tested in UVM regression environment and has been interoperability tested with key ADC/DAC providers and leading Serdes/PHY solutions.
Key Features
- Delivering Performance
- Designed to JEDEC JESD204C specification
- Line rates from 1 Gb/s to 32 Gb/s
- Supports 1-24 lanes
- Supports 1-32 converters
- HD-mode supported
- Performs user-enabled scrambling
- Generates initial lane alignment sequence
- Performs the alignment character generation
- Sources link configuration data with user selected parameter values during initial lane synchronization sequence
- 8B/10B, 64B/66B, 64B/80B encoding/decoding supported
- Verilog-based
- Optional data mapping and de-mapping
- Supports Subclasses 0, 1, and 2
- Internal clock generation
Easy to use
- HW demonstration platform available
- VIP and regression test suite available
- SerDes interoperability with several major vendors
- Simple test bench is included
- Designed in Verilog and targeting any RTL implementation like ASICs, ASSPs and FPGAs.
Applications
High speed data arcquisition systems
- Wireless infrastructure transceiver architectures
- Radar systems
- Software-defined radios
- Portable instrumentation
- Medical ultrasound equipment
Interoperability
- JESD204C IP has been interoperability tested with Analog Devices JESD204C implementation