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Layout IP Cores EDA Layout Training Consultancy Analog/Mix Design Turnkey ASIC

ONLINE Design for Layout Course June27th, 2022

 

By ICMASK Design's CTO Mr. Ciaran Whyte 

Dear ,

 

ICMASK will perform Design for Layout Course remotely/online.  It will be delivered in 4 days x 4 hour sessions by the most professional layout guru the CTO of ICMSAK Design Mr. Ciaran Whyte on June 27th 2022, for 4 days.

 

IC Mask Design’s “Design for Layout” course has taken 20+ years of working with over 250 different
Design teams and distilled this experience into a short course that examines how Layout and Design can
be married together so that Circuit Designers can design their circuits with Layout in mind while still not
impacting circuit performance. The course looks at real tips on how to improve Layout efficiency and
reduce costly layout tuning cycles.

 

Audience: 

This is geared towards Design teams working with Layout teams trying to produce quality layouts in the
shortest possible time.

 

Agenda:

Day 1:

  • THE MOS TRANSISTOR & CMOS CIRCUITS
    • Improving Layout efficiency through MOS design.
    • Optimising MOS for layout and silicon quality.
    • Tips and tricks – accelerate the layout process & reduce tuning cycles.
  • LAYOUT DEPENDENT EFFECTS
    • Understanding LDEs – impact on layout and design.
      • Should you really share devices? Fold? Add rings?...
    • How to design out the impacts of LDE at design stage.
      • A design driven layout methodology to lessen the impacts of LDE.

Day 2:

  • PASSIVE DEVICES
    • Optimising Q, reducing device parasitics and area, through layout techniques and design intent.
    • Shielding passives and what not to do.
  • DESIGN FOR DENSITY
    • A design driven approach for density clean layouts, by construction.
    • Device size/shape choice; metal stacks; impacts of design decisions on density.

Day 3:

  • DEVICE MATCHING
    • Myth busting – common mis held assumptions, that can unnecessarily constrain layout.
    • Optimising designs for matching at a specific technology node.
    • Creating schematics that can be matched, with ease – accelerate the layout process.
    • What not to give to the layout engineer.

Day 4:

  • DESIGN DECISIONS VS SILICON RISK
    • Avoiding common design decisions (mistakes) that can lead to risk of silicon failure.
    • Latchup, DFM/Yield
  • DESIGN INTENT
    • The traditional design wall – and it’s evolution.
    • How to communicate design intent and achieve best class results in layout.

Should you seek more information do not hesitate to contact us @ akatav@kaltech.co.il or click bellow

Info Request

Resources we think you might like:

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Certus Semiconductor the ESD & IOs company

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JESD204C controller - IP Overview

Ethernet 1G/2.5G/5G/10G/25G and CPRI 7.0 PCS - IP Overview

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The D32PRO is a royalty-free, silicon proven, high performance soft core of a single-chip 32-bit embedded controller, with Floating Point Coprocessor

Electronic Design Debug – EDA Tools

 

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IC Mask Design: Combining innovation and unrivalled engineering knowledge

Electronic Design Debugging Tools for Analog, Digital, AMS and SoC Designers

StarVision® PRO: A Customizable Mixed‐Signal Debugging Platform

END-TO-END IC Layout Services By ICMASK

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Kiryat Ono, Israel 5510602  

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