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Layout IP Cores EDA Layout Training Consultancy Analog/Mix Design Turnkey ASIC

ONLINE RF Layout Course May 30th, 2022

 

By ICMASK Design's CTO Mr. Ciaran Whyte 

Dear ,

 

ICMASK will perform RF Layout Course remotely/online.  It will be delivered in 4 days x 4 hour sessions by the most professional layout guru the CTO of ICMSAK Design Mr. Ciaran Whyte on May 30th  to June 2nd(4 days) 2022

 

IC Mask Designs RF Layout course looks at the many challenges involved in producing layouts
that are expected to operate in the multiple GHz frequency range and more specifically, in the
layout of circuits used in radio transceivers on bulk CMOS processes. This deep dive into the
many layout challenges is accompanied by presenting practical real-life solutions, that can be
implemented in layout, enabling the layout engineer to produce high speed, high-quality
layouts, in compressed time scales.

 

Target Audience: 

 

Any layout or design engineer looking to create layouts of very high-speed (multiple GHz)
circuits would benefit from participation on this course. It looks to build on and fine-tune
techniques commonly applied in core analog layout, so that they are optimised with
device and interconnect parasitics in mind.

 

DAY 1: 

Understanding the impacts of layout parasitics on circuit design

Base layers in a CMOS process – the capacitive effects of P/N Junctions & dielectric
behaviour of substrate.

Metal Interconnect – The 3 types of parasitic capacitance.

Interconnect resistance & impedance.

Compromises and constraints – capacitance over resistance, capacitance over area, etc.

 

DAY 2: 

Understanding parasitic extraction – the different approaches (lumped,
distributed, 2.5D, 3D).

Reducing parasitic tuning cycles (developing and utilising look up tables)

The risks and advantages of device and interconnect shielding – when not to do it, and
how to do to it correctly.

Device parasitics, optimising Q.

 

DAY 3:

Inductor and varactor layout, device layout, and floorplanning considerations.

Device matching @ RF – the compromises (parasitic vs. matching).

Supply considerations – noise, EM and IR drop.

 

DAY 4:

Substrate noise isolation – what’s different at RF

Introduction to the superheterodyne transceiver

Layout issues of common RF building blocks (LNA, Down Mixer, LC Tank VCO,
Divider, Up Mixer & TX Amp)

 

Should you seek more information do not hesitate to contact us @ akatav@kaltech.co.il or click bellow

 

Next course: Design for Layout on June 27th

Info Request

Resources we think you might like:

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Certus Semiconductor the ESD & IOs company

Shorting Source to Bulk – Adding Risk to Silicon? (Article)

JESD204C controller - IP Overview

Ethernet 1G/2.5G/5G/10G/25G and CPRI 7.0 PCS - IP Overview

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The D32PRO is a royalty-free, silicon proven, high performance soft core of a single-chip 32-bit embedded controller, with Floating Point Coprocessor

Electronic Design Debug – EDA Tools

 

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IC Mask Design: Combining innovation and unrivalled engineering knowledge

Electronic Design Debugging Tools for Analog, Digital, AMS and SoC Designers

StarVision® PRO: A Customizable Mixed‐Signal Debugging Platform

END-TO-END IC Layout Services By ICMASK

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Kiryat Ono, Israel 5510602  

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