Overview
The Interlaken IP coreby our partner Comcores is a highly optimized silicon and PHY agnostic implementation of the Interlaken Protocol version 1.2 targeting both ASICs and FPGAs. Our Interlaken controller supports up to 2.6Tbps high-bandwidth performance and comes with an integrated Media Access layer.
The IP can be widely used in chip-to-chip transfers, it has an extensive feature-set available and allows scalability in both number of lanes and lane speed. The IP core is heavily tested in SystemVerilog random regression environment.
Key Features
Richly Featured
MAC layer with fast AMBA CXS interface
PCS layer highly configurable
64b67b encoding/decoding supported
Solid
SystemVerilog random regression tested
Lint/CDC checked
Easy to use
Solid documentation including integration guide
Easy to use RTL test environment
No special software required
Strong engineering support for bring-up
Silicon Agnostic
Targeting both ASICs and FPGAs
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
Solid documentation, including User Manual, Release Note and Quick Start Guide.
Simulation Environment, including Simple Testbed, Test case, Test Script.
Programming Register Specification.
Timing Constraints in Synopsys SDC format.
Access to support system and direct support from Comcores Engineers.
Test Report (optional)
Synopsys SGDC Files (optional)
Synopsys Lint, CDC and Waivers (optional)