IP Review - 4 Channels DMA Dear ,
Today we would like to intro a well known IP core that got some update and already silicon proven:
The 4 Channels DMA is a four-channel Direct Memory Access Controller. Its purpose is to transfer data between memories and peripherals to reduce CPU utilization during data transfers. It can be programmed by the CPU via a 32-bit or 8-bit native interface. The DMA can perform data transactions of configurable size over 32-bit address space. A single transaction size can be set in a range from 1B to 16MB. To limit the negative impact of different reads and writes timing the DMA features transfer data buffer. This buffer is a 32-bit FIFO memory with configurable depth.
Data transactions can be triggered either by hardware or software. Hardware initialization is achieved via the Peripheral Request Interface, while software initialization is done by the CPU via registers. The Peripheral Request Interface is used by external controllers (peripherals) to set data transaction requests on specific DMA channel. Each of the DMA channels has a set of Peripheral Request Interface signals associated with it. Peripherals can request the transmission or reception of data. When multiple channels await data transfer the arbitration process utilizes a round-robin algorithm.
There are four DMA channels. Each has its configuration registers and enable bit.
The DMA offers three transfer modes: - SINGLE – single data transfer on request,
- NORMAL – one data block transfer on request,
- BLOCK – all data blocks transfer on request.
KEY FEATURES - 32-bit or 8-bit internal registers access
- 32-bit transmission address range
- Transaction size from 1B up to 16MB
- Four transmission channels
- Round-robin arbitration
- Data buffer with configurable size
- For each channel:
- Enable bit
- Software transmission request
- Peripheral request interface:
- Transmission request
- Single data transmission request
- Reception request
- Single data reception request
- Configurable request clear signal
- Transfer status flags:
- Transaction finished
- Block finished
- Single data finished
- Transfer status flags maskable interrupts
- Three transfer modes:
- Independently configurable source and destination data width:
- Configurable source and destination base addresses
- Three addressing modes: INC, DEC, FIXED
- Three sources and destination address reload options each:
- Transaction divided into blocks
- Configurable transfer size: including amount of blocks and blocks size
- Double buffered address, block and byte registers
- Available DMA interface wrappers:
- Native 32-bit interface
- AMBA – APB / AHB / AXI Lite
- Software reset
-
Configurable hardware reset
- Fully synthesizable
- No internal tri-states
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